A high-speed serial receiver samples incoming data symbols at some phase of the high-speed clock generated from the PLL. The PLL uses a reference clock to produce the high-speed clock. The edge transitions (recovered clock) between incoming data symbols can be recovered using the high-speed clock. To properly sample the incoming data symbols, the receiver should sample the incoming data symbols between the edge transitions in the stream of incoming data symbols. The range of sampling phases for which the high-speed serial receiver properly recovers the incoming data symbols gives the margin for the sampling phase.
To check the margin of the sampling phase, external test equipment can inject sinusoidal jitter or bounded uncorrelated jitter (BUJ) into the timing of data symbols sent to the high-speed serial receiver. The high-speed serial receiver recovers the sampling clock from the incoming data symbols using a low-pass filter that rejects injected jitter placed above the cut-off frequency of the low-pass filter. Thus, the injected jitter can vary the timing of the data symbols without appreciably affecting the timing of the recovered sampling clock. The range of magnitudes of the injected jitter for which the high-speed serial receiver properly recovers the data symbols gives the margin of the sampling phase. To check that the data symbols actually captured by the high-speed serial receiver match the data symbols that the external test equipment transmits to the high-speed serial receiver, the captured data symbols must be looped back to the external test equipment.
It is time consuming and difficult to determine the margin of the sampling phase because external test equipment is required and because the tested receiver must generally include a transmitter supporting a loopback mode for returning the actually captured data symbols back to the external test equipment.